-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 11.0 Build 208 07/03/2011 Service Pack 1 SJ Full Version"

-- DATE "02/21/2012 15:39:44"

-- 
-- Device: Altera EP3C16F484C8 Package FBGA484
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	my_pwm IS
    PORT (
	pwm_out_grip : OUT std_logic;
	clk : IN std_logic;
	duty_cycle_grip : IN std_logic_vector(7 DOWNTO 0);
	pwm_enable : IN std_logic;
	resetn : IN std_logic
	);
END my_pwm;

-- Design Ports Information
-- pwm_enable	=>  Location: PIN_D2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- pwm_out_grip	=>  Location: PIN_E4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- duty_cycle_grip[7]	=>  Location: PIN_B22,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- clk	=>  Location: PIN_G21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- resetn	=>  Location: PIN_H2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- duty_cycle_grip[6]	=>  Location: PIN_C6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- duty_cycle_grip[5]	=>  Location: PIN_C1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- duty_cycle_grip[4]	=>  Location: PIN_E1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- duty_cycle_grip[3]	=>  Location: PIN_G4,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- duty_cycle_grip[2]	=>  Location: PIN_H6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- duty_cycle_grip[1]	=>  Location: PIN_E3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- duty_cycle_grip[0]	=>  Location: PIN_H7,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF my_pwm IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_pwm_out_grip : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_duty_cycle_grip : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_pwm_enable : std_logic;
SIGNAL ww_resetn : std_logic;
SIGNAL \slow_clk~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \counter[4]~13_combout\ : std_logic;
SIGNAL \counter[5]~16\ : std_logic;
SIGNAL \counter[6]~18\ : std_logic;
SIGNAL \counter[6]~17_combout\ : std_logic;
SIGNAL \counter[7]~19_combout\ : std_logic;
SIGNAL \Add0~12_combout\ : std_logic;
SIGNAL \Add0~22_combout\ : std_logic;
SIGNAL \Add0~29\ : std_logic;
SIGNAL \Add0~30_combout\ : std_logic;
SIGNAL \Equal0~1_combout\ : std_logic;
SIGNAL \clock_div~0_combout\ : std_logic;
SIGNAL \pwm_enable~input_o\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \duty_cycle_grip[5]~input_o\ : std_logic;
SIGNAL \duty_cycle_grip[2]~input_o\ : std_logic;
SIGNAL \duty_cycle_grip[0]~input_o\ : std_logic;
SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
SIGNAL \Add0~0_combout\ : std_logic;
SIGNAL \clock_div~3_combout\ : std_logic;
SIGNAL \resetn~input_o\ : std_logic;
SIGNAL \Add0~1\ : std_logic;
SIGNAL \Add0~2_combout\ : std_logic;
SIGNAL \Add0~3\ : std_logic;
SIGNAL \Add0~5\ : std_logic;
SIGNAL \Add0~7\ : std_logic;
SIGNAL \Add0~8_combout\ : std_logic;
SIGNAL \Add0~9\ : std_logic;
SIGNAL \Add0~10_combout\ : std_logic;
SIGNAL \clock_div~1_combout\ : std_logic;
SIGNAL \Add0~11\ : std_logic;
SIGNAL \Add0~13\ : std_logic;
SIGNAL \Add0~14_combout\ : std_logic;
SIGNAL \Equal0~2_combout\ : std_logic;
SIGNAL \Add0~15\ : std_logic;
SIGNAL \Add0~16_combout\ : std_logic;
SIGNAL \Add0~17\ : std_logic;
SIGNAL \Add0~18_combout\ : std_logic;
SIGNAL \Add0~19\ : std_logic;
SIGNAL \Add0~20_combout\ : std_logic;
SIGNAL \Add0~21\ : std_logic;
SIGNAL \Add0~23\ : std_logic;
SIGNAL \Add0~24_combout\ : std_logic;
SIGNAL \Add0~25\ : std_logic;
SIGNAL \Add0~27\ : std_logic;
SIGNAL \Add0~28_combout\ : std_logic;
SIGNAL \Add0~26_combout\ : std_logic;
SIGNAL \Equal0~0_combout\ : std_logic;
SIGNAL \Add0~4_combout\ : std_logic;
SIGNAL \clock_div~2_combout\ : std_logic;
SIGNAL \Add0~6_combout\ : std_logic;
SIGNAL \Equal0~3_combout\ : std_logic;
SIGNAL \Equal0~4_combout\ : std_logic;
SIGNAL \slow_clk~0_combout\ : std_logic;
SIGNAL \slow_clk~feeder_combout\ : std_logic;
SIGNAL \slow_clk~q\ : std_logic;
SIGNAL \slow_clk~clkctrl_outclk\ : std_logic;
SIGNAL \duty_cycle_grip[7]~input_o\ : std_logic;
SIGNAL \duty_cycle_reg_grip[7]~feeder_combout\ : std_logic;
SIGNAL \duty_cycle_grip[6]~input_o\ : std_logic;
SIGNAL \counter[1]~7_combout\ : std_logic;
SIGNAL \counter[1]~8\ : std_logic;
SIGNAL \counter[2]~9_combout\ : std_logic;
SIGNAL \counter[2]~10\ : std_logic;
SIGNAL \counter[3]~11_combout\ : std_logic;
SIGNAL \counter[3]~12\ : std_logic;
SIGNAL \counter[4]~14\ : std_logic;
SIGNAL \counter[5]~15_combout\ : std_logic;
SIGNAL \duty_cycle_grip[4]~input_o\ : std_logic;
SIGNAL \duty_cycle_grip[3]~input_o\ : std_logic;
SIGNAL \duty_cycle_grip[1]~input_o\ : std_logic;
SIGNAL \counter[0]~21_combout\ : std_logic;
SIGNAL \LessThan0~1_cout\ : std_logic;
SIGNAL \LessThan0~3_cout\ : std_logic;
SIGNAL \LessThan0~5_cout\ : std_logic;
SIGNAL \LessThan0~7_cout\ : std_logic;
SIGNAL \LessThan0~9_cout\ : std_logic;
SIGNAL \LessThan0~11_cout\ : std_logic;
SIGNAL \LessThan0~13_cout\ : std_logic;
SIGNAL \LessThan0~14_combout\ : std_logic;
SIGNAL \pwm_out_reg_grip~q\ : std_logic;
SIGNAL clock_div : std_logic_vector(15 DOWNTO 0);
SIGNAL counter : std_logic_vector(7 DOWNTO 0);
SIGNAL duty_cycle_reg_grip : std_logic_vector(7 DOWNTO 0);

BEGIN

pwm_out_grip <= ww_pwm_out_grip;
ww_clk <= clk;
ww_duty_cycle_grip <= duty_cycle_grip;
ww_pwm_enable <= pwm_enable;
ww_resetn <= resetn;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\slow_clk~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \slow_clk~q\);

\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);

-- Location: FF_X5_Y26_N13
\counter[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \slow_clk~clkctrl_outclk\,
	d => \counter[7]~19_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => counter(7));

-- Location: FF_X5_Y26_N11
\counter[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \slow_clk~clkctrl_outclk\,
	d => \counter[6]~17_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => counter(6));

-- Location: FF_X5_Y26_N7
\counter[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \slow_clk~clkctrl_outclk\,
	d => \counter[4]~13_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => counter(4));

-- Location: LCCOMB_X5_Y26_N6
\counter[4]~13\ : cycloneiii_lcell_comb
-- Equation(s):
-- \counter[4]~13_combout\ = (counter(4) & (!\counter[3]~12\)) # (!counter(4) & ((\counter[3]~12\) # (GND)))
-- \counter[4]~14\ = CARRY((!\counter[3]~12\) # (!counter(4)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => counter(4),
	datad => VCC,
	cin => \counter[3]~12\,
	combout => \counter[4]~13_combout\,
	cout => \counter[4]~14\);

-- Location: LCCOMB_X5_Y26_N8
\counter[5]~15\ : cycloneiii_lcell_comb
-- Equation(s):
-- \counter[5]~15_combout\ = (counter(5) & (\counter[4]~14\ $ (GND))) # (!counter(5) & (!\counter[4]~14\ & VCC))
-- \counter[5]~16\ = CARRY((counter(5) & !\counter[4]~14\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => counter(5),
	datad => VCC,
	cin => \counter[4]~14\,
	combout => \counter[5]~15_combout\,
	cout => \counter[5]~16\);

-- Location: LCCOMB_X5_Y26_N10
\counter[6]~17\ : cycloneiii_lcell_comb
-- Equation(s):
-- \counter[6]~17_combout\ = (counter(6) & (!\counter[5]~16\)) # (!counter(6) & ((\counter[5]~16\) # (GND)))
-- \counter[6]~18\ = CARRY((!\counter[5]~16\) # (!counter(6)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => counter(6),
	datad => VCC,
	cin => \counter[5]~16\,
	combout => \counter[6]~17_combout\,
	cout => \counter[6]~18\);

-- Location: LCCOMB_X5_Y26_N12
\counter[7]~19\ : cycloneiii_lcell_comb
-- Equation(s):
-- \counter[7]~19_combout\ = \counter[6]~18\ $ (!counter(7))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000001111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => counter(7),
	cin => \counter[6]~18\,
	combout => \counter[7]~19_combout\);

-- Location: LCCOMB_X22_Y28_N12
\Add0~12\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~12_combout\ = (clock_div(6) & (\Add0~11\ $ (GND))) # (!clock_div(6) & (!\Add0~11\ & VCC))
-- \Add0~13\ = CARRY((clock_div(6) & !\Add0~11\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => clock_div(6),
	datad => VCC,
	cin => \Add0~11\,
	combout => \Add0~12_combout\,
	cout => \Add0~13\);

-- Location: LCCOMB_X22_Y28_N22
\Add0~22\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~22_combout\ = (clock_div(11) & (!\Add0~21\)) # (!clock_div(11) & ((\Add0~21\) # (GND)))
-- \Add0~23\ = CARRY((!\Add0~21\) # (!clock_div(11)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => clock_div(11),
	datad => VCC,
	cin => \Add0~21\,
	combout => \Add0~22_combout\,
	cout => \Add0~23\);

-- Location: LCCOMB_X22_Y28_N28
\Add0~28\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~28_combout\ = (clock_div(14) & (\Add0~27\ $ (GND))) # (!clock_div(14) & (!\Add0~27\ & VCC))
-- \Add0~29\ = CARRY((clock_div(14) & !\Add0~27\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => clock_div(14),
	datad => VCC,
	cin => \Add0~27\,
	combout => \Add0~28_combout\,
	cout => \Add0~29\);

-- Location: LCCOMB_X22_Y28_N30
\Add0~30\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~30_combout\ = \Add0~29\ $ (clock_div(15))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => clock_div(15),
	cin => \Add0~29\,
	combout => \Add0~30_combout\);

-- Location: FF_X5_Y26_N27
\duty_cycle_reg_grip[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \duty_cycle_grip[5]~input_o\,
	sload => VCC,
	ena => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => duty_cycle_reg_grip(5));

-- Location: FF_X5_Y26_N21
\duty_cycle_reg_grip[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \duty_cycle_grip[2]~input_o\,
	sload => VCC,
	ena => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => duty_cycle_reg_grip(2));

-- Location: FF_X5_Y26_N17
\duty_cycle_reg_grip[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \duty_cycle_grip[0]~input_o\,
	sload => VCC,
	ena => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => duty_cycle_reg_grip(0));

-- Location: FF_X22_Y28_N31
\clock_div[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~30_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(15));

-- Location: FF_X22_Y28_N23
\clock_div[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~22_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(11));

-- Location: LCCOMB_X21_Y28_N12
\Equal0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~1_combout\ = (!clock_div(10) & (!clock_div(9) & (!clock_div(11) & !clock_div(8))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => clock_div(10),
	datab => clock_div(9),
	datac => clock_div(11),
	datad => clock_div(8),
	combout => \Equal0~1_combout\);

-- Location: FF_X21_Y28_N11
\clock_div[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \clock_div~0_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(6));

-- Location: LCCOMB_X21_Y28_N10
\clock_div~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \clock_div~0_combout\ = (\Add0~12_combout\ & !\Equal0~4_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \Add0~12_combout\,
	datad => \Equal0~4_combout\,
	combout => \clock_div~0_combout\);

-- Location: IOIBUF_X41_Y15_N1
\clk~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_clk,
	o => \clk~input_o\);

-- Location: IOIBUF_X0_Y26_N22
\duty_cycle_grip[5]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_duty_cycle_grip(5),
	o => \duty_cycle_grip[5]~input_o\);

-- Location: IOIBUF_X0_Y25_N22
\duty_cycle_grip[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_duty_cycle_grip(2),
	o => \duty_cycle_grip[2]~input_o\);

-- Location: IOIBUF_X0_Y25_N15
\duty_cycle_grip[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_duty_cycle_grip(0),
	o => \duty_cycle_grip[0]~input_o\);

-- Location: CLKCTRL_G9
\clk~inputclkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \clk~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~inputclkctrl_outclk\);

-- Location: IOOBUF_X0_Y26_N2
\pwm_out_grip~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \pwm_out_reg_grip~q\,
	devoe => ww_devoe,
	o => ww_pwm_out_grip);

-- Location: LCCOMB_X22_Y28_N0
\Add0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~0_combout\ = clock_div(0) $ (VCC)
-- \Add0~1\ = CARRY(clock_div(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => clock_div(0),
	datad => VCC,
	combout => \Add0~0_combout\,
	cout => \Add0~1\);

-- Location: LCCOMB_X21_Y28_N6
\clock_div~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \clock_div~3_combout\ = (\Add0~0_combout\ & !\Equal0~4_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \Add0~0_combout\,
	datad => \Equal0~4_combout\,
	combout => \clock_div~3_combout\);

-- Location: IOIBUF_X0_Y21_N8
\resetn~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_resetn,
	o => \resetn~input_o\);

-- Location: FF_X21_Y28_N7
\clock_div[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \clock_div~3_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(0));

-- Location: LCCOMB_X22_Y28_N2
\Add0~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~2_combout\ = (clock_div(1) & (!\Add0~1\)) # (!clock_div(1) & ((\Add0~1\) # (GND)))
-- \Add0~3\ = CARRY((!\Add0~1\) # (!clock_div(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => clock_div(1),
	datad => VCC,
	cin => \Add0~1\,
	combout => \Add0~2_combout\,
	cout => \Add0~3\);

-- Location: FF_X22_Y28_N3
\clock_div[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~2_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(1));

-- Location: LCCOMB_X22_Y28_N4
\Add0~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~4_combout\ = (clock_div(2) & (\Add0~3\ $ (GND))) # (!clock_div(2) & (!\Add0~3\ & VCC))
-- \Add0~5\ = CARRY((clock_div(2) & !\Add0~3\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => clock_div(2),
	datad => VCC,
	cin => \Add0~3\,
	combout => \Add0~4_combout\,
	cout => \Add0~5\);

-- Location: LCCOMB_X22_Y28_N6
\Add0~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~6_combout\ = (clock_div(3) & (!\Add0~5\)) # (!clock_div(3) & ((\Add0~5\) # (GND)))
-- \Add0~7\ = CARRY((!\Add0~5\) # (!clock_div(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => clock_div(3),
	datad => VCC,
	cin => \Add0~5\,
	combout => \Add0~6_combout\,
	cout => \Add0~7\);

-- Location: LCCOMB_X22_Y28_N8
\Add0~8\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~8_combout\ = (clock_div(4) & (\Add0~7\ $ (GND))) # (!clock_div(4) & (!\Add0~7\ & VCC))
-- \Add0~9\ = CARRY((clock_div(4) & !\Add0~7\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => clock_div(4),
	datad => VCC,
	cin => \Add0~7\,
	combout => \Add0~8_combout\,
	cout => \Add0~9\);

-- Location: FF_X22_Y28_N9
\clock_div[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~8_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(4));

-- Location: LCCOMB_X22_Y28_N10
\Add0~10\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~10_combout\ = (clock_div(5) & (!\Add0~9\)) # (!clock_div(5) & ((\Add0~9\) # (GND)))
-- \Add0~11\ = CARRY((!\Add0~9\) # (!clock_div(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => clock_div(5),
	datad => VCC,
	cin => \Add0~9\,
	combout => \Add0~10_combout\,
	cout => \Add0~11\);

-- Location: LCCOMB_X21_Y28_N24
\clock_div~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \clock_div~1_combout\ = (\Add0~10_combout\ & !\Equal0~4_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \Add0~10_combout\,
	datad => \Equal0~4_combout\,
	combout => \clock_div~1_combout\);

-- Location: FF_X21_Y28_N25
\clock_div[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \clock_div~1_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(5));

-- Location: LCCOMB_X22_Y28_N14
\Add0~14\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~14_combout\ = (clock_div(7) & (!\Add0~13\)) # (!clock_div(7) & ((\Add0~13\) # (GND)))
-- \Add0~15\ = CARRY((!\Add0~13\) # (!clock_div(7)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => clock_div(7),
	datad => VCC,
	cin => \Add0~13\,
	combout => \Add0~14_combout\,
	cout => \Add0~15\);

-- Location: FF_X22_Y28_N15
\clock_div[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~14_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(7));

-- Location: LCCOMB_X21_Y28_N4
\Equal0~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~2_combout\ = (clock_div(6) & (!clock_div(4) & (!clock_div(7) & clock_div(5))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => clock_div(6),
	datab => clock_div(4),
	datac => clock_div(7),
	datad => clock_div(5),
	combout => \Equal0~2_combout\);

-- Location: LCCOMB_X22_Y28_N16
\Add0~16\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~16_combout\ = (clock_div(8) & (\Add0~15\ $ (GND))) # (!clock_div(8) & (!\Add0~15\ & VCC))
-- \Add0~17\ = CARRY((clock_div(8) & !\Add0~15\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => clock_div(8),
	datad => VCC,
	cin => \Add0~15\,
	combout => \Add0~16_combout\,
	cout => \Add0~17\);

-- Location: FF_X22_Y28_N17
\clock_div[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~16_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(8));

-- Location: LCCOMB_X22_Y28_N18
\Add0~18\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~18_combout\ = (clock_div(9) & (!\Add0~17\)) # (!clock_div(9) & ((\Add0~17\) # (GND)))
-- \Add0~19\ = CARRY((!\Add0~17\) # (!clock_div(9)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => clock_div(9),
	datad => VCC,
	cin => \Add0~17\,
	combout => \Add0~18_combout\,
	cout => \Add0~19\);

-- Location: FF_X22_Y28_N19
\clock_div[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~18_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(9));

-- Location: LCCOMB_X22_Y28_N20
\Add0~20\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~20_combout\ = (clock_div(10) & (\Add0~19\ $ (GND))) # (!clock_div(10) & (!\Add0~19\ & VCC))
-- \Add0~21\ = CARRY((clock_div(10) & !\Add0~19\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => clock_div(10),
	datad => VCC,
	cin => \Add0~19\,
	combout => \Add0~20_combout\,
	cout => \Add0~21\);

-- Location: FF_X22_Y28_N21
\clock_div[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~20_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(10));

-- Location: LCCOMB_X22_Y28_N24
\Add0~24\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~24_combout\ = (clock_div(12) & (\Add0~23\ $ (GND))) # (!clock_div(12) & (!\Add0~23\ & VCC))
-- \Add0~25\ = CARRY((clock_div(12) & !\Add0~23\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => clock_div(12),
	datad => VCC,
	cin => \Add0~23\,
	combout => \Add0~24_combout\,
	cout => \Add0~25\);

-- Location: FF_X22_Y28_N25
\clock_div[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~24_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(12));

-- Location: LCCOMB_X22_Y28_N26
\Add0~26\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~26_combout\ = (clock_div(13) & (!\Add0~25\)) # (!clock_div(13) & ((\Add0~25\) # (GND)))
-- \Add0~27\ = CARRY((!\Add0~25\) # (!clock_div(13)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => clock_div(13),
	datad => VCC,
	cin => \Add0~25\,
	combout => \Add0~26_combout\,
	cout => \Add0~27\);

-- Location: FF_X22_Y28_N29
\clock_div[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~28_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(14));

-- Location: FF_X22_Y28_N27
\clock_div[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~26_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(13));

-- Location: LCCOMB_X21_Y28_N26
\Equal0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~0_combout\ = (!clock_div(15) & (!clock_div(14) & (!clock_div(13) & !clock_div(12))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => clock_div(15),
	datab => clock_div(14),
	datac => clock_div(13),
	datad => clock_div(12),
	combout => \Equal0~0_combout\);

-- Location: LCCOMB_X21_Y28_N16
\clock_div~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \clock_div~2_combout\ = (!\Equal0~4_combout\ & \Add0~4_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \Equal0~4_combout\,
	datad => \Add0~4_combout\,
	combout => \clock_div~2_combout\);

-- Location: FF_X21_Y28_N17
\clock_div[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \clock_div~2_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(2));

-- Location: FF_X22_Y28_N7
\clock_div[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~6_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => clock_div(3));

-- Location: LCCOMB_X21_Y28_N18
\Equal0~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~3_combout\ = (!clock_div(0) & (clock_div(2) & (!clock_div(1) & !clock_div(3))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => clock_div(0),
	datab => clock_div(2),
	datac => clock_div(1),
	datad => clock_div(3),
	combout => \Equal0~3_combout\);

-- Location: LCCOMB_X21_Y28_N20
\Equal0~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~4_combout\ = (\Equal0~1_combout\ & (\Equal0~2_combout\ & (\Equal0~0_combout\ & \Equal0~3_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Equal0~1_combout\,
	datab => \Equal0~2_combout\,
	datac => \Equal0~0_combout\,
	datad => \Equal0~3_combout\,
	combout => \Equal0~4_combout\);

-- Location: LCCOMB_X21_Y28_N22
\slow_clk~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \slow_clk~0_combout\ = \slow_clk~q\ $ (\Equal0~4_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \slow_clk~q\,
	datad => \Equal0~4_combout\,
	combout => \slow_clk~0_combout\);

-- Location: LCCOMB_X21_Y28_N14
\slow_clk~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \slow_clk~feeder_combout\ = \slow_clk~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100110011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \slow_clk~0_combout\,
	combout => \slow_clk~feeder_combout\);

-- Location: FF_X21_Y28_N15
slow_clk : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \slow_clk~feeder_combout\,
	clrn => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \slow_clk~q\);

-- Location: CLKCTRL_G19
\slow_clk~clkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \slow_clk~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \slow_clk~clkctrl_outclk\);

-- Location: IOIBUF_X41_Y26_N8
\duty_cycle_grip[7]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_duty_cycle_grip(7),
	o => \duty_cycle_grip[7]~input_o\);

-- Location: LCCOMB_X21_Y28_N28
\duty_cycle_reg_grip[7]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \duty_cycle_reg_grip[7]~feeder_combout\ = \duty_cycle_grip[7]~input_o\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \duty_cycle_grip[7]~input_o\,
	combout => \duty_cycle_reg_grip[7]~feeder_combout\);

-- Location: FF_X21_Y28_N29
\duty_cycle_reg_grip[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \duty_cycle_reg_grip[7]~feeder_combout\,
	ena => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => duty_cycle_reg_grip(7));

-- Location: IOIBUF_X5_Y29_N1
\duty_cycle_grip[6]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_duty_cycle_grip(6),
	o => \duty_cycle_grip[6]~input_o\);

-- Location: FF_X5_Y26_N29
\duty_cycle_reg_grip[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \duty_cycle_grip[6]~input_o\,
	sload => VCC,
	ena => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => duty_cycle_reg_grip(6));

-- Location: LCCOMB_X5_Y26_N0
\counter[1]~7\ : cycloneiii_lcell_comb
-- Equation(s):
-- \counter[1]~7_combout\ = (counter(0) & (counter(1) $ (VCC))) # (!counter(0) & (counter(1) & VCC))
-- \counter[1]~8\ = CARRY((counter(0) & counter(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110011010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => counter(0),
	datab => counter(1),
	datad => VCC,
	combout => \counter[1]~7_combout\,
	cout => \counter[1]~8\);

-- Location: FF_X5_Y26_N1
\counter[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \slow_clk~clkctrl_outclk\,
	d => \counter[1]~7_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => counter(1));

-- Location: LCCOMB_X5_Y26_N2
\counter[2]~9\ : cycloneiii_lcell_comb
-- Equation(s):
-- \counter[2]~9_combout\ = (counter(2) & (!\counter[1]~8\)) # (!counter(2) & ((\counter[1]~8\) # (GND)))
-- \counter[2]~10\ = CARRY((!\counter[1]~8\) # (!counter(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => counter(2),
	datad => VCC,
	cin => \counter[1]~8\,
	combout => \counter[2]~9_combout\,
	cout => \counter[2]~10\);

-- Location: FF_X5_Y26_N3
\counter[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \slow_clk~clkctrl_outclk\,
	d => \counter[2]~9_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => counter(2));

-- Location: LCCOMB_X5_Y26_N4
\counter[3]~11\ : cycloneiii_lcell_comb
-- Equation(s):
-- \counter[3]~11_combout\ = (counter(3) & (\counter[2]~10\ $ (GND))) # (!counter(3) & (!\counter[2]~10\ & VCC))
-- \counter[3]~12\ = CARRY((counter(3) & !\counter[2]~10\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => counter(3),
	datad => VCC,
	cin => \counter[2]~10\,
	combout => \counter[3]~11_combout\,
	cout => \counter[3]~12\);

-- Location: FF_X5_Y26_N5
\counter[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \slow_clk~clkctrl_outclk\,
	d => \counter[3]~11_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => counter(3));

-- Location: FF_X5_Y26_N9
\counter[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \slow_clk~clkctrl_outclk\,
	d => \counter[5]~15_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => counter(5));

-- Location: IOIBUF_X0_Y24_N15
\duty_cycle_grip[4]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_duty_cycle_grip(4),
	o => \duty_cycle_grip[4]~input_o\);

-- Location: FF_X5_Y26_N25
\duty_cycle_reg_grip[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \duty_cycle_grip[4]~input_o\,
	sload => VCC,
	ena => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => duty_cycle_reg_grip(4));

-- Location: IOIBUF_X0_Y23_N8
\duty_cycle_grip[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_duty_cycle_grip(3),
	o => \duty_cycle_grip[3]~input_o\);

-- Location: FF_X5_Y26_N23
\duty_cycle_reg_grip[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \duty_cycle_grip[3]~input_o\,
	sload => VCC,
	ena => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => duty_cycle_reg_grip(3));

-- Location: IOIBUF_X0_Y26_N8
\duty_cycle_grip[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_duty_cycle_grip(1),
	o => \duty_cycle_grip[1]~input_o\);

-- Location: FF_X5_Y26_N19
\duty_cycle_reg_grip[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \duty_cycle_grip[1]~input_o\,
	sload => VCC,
	ena => \resetn~input_o\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => duty_cycle_reg_grip(1));

-- Location: LCCOMB_X5_Y26_N14
\counter[0]~21\ : cycloneiii_lcell_comb
-- Equation(s):
-- \counter[0]~21_combout\ = !counter(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => counter(0),
	combout => \counter[0]~21_combout\);

-- Location: FF_X5_Y26_N15
\counter[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \slow_clk~clkctrl_outclk\,
	d => \counter[0]~21_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => counter(0));

-- Location: LCCOMB_X5_Y26_N16
\LessThan0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~1_cout\ = CARRY((duty_cycle_reg_grip(0) & !counter(0)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000100010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => duty_cycle_reg_grip(0),
	datab => counter(0),
	datad => VCC,
	cout => \LessThan0~1_cout\);

-- Location: LCCOMB_X5_Y26_N18
\LessThan0~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~3_cout\ = CARRY((counter(1) & ((!\LessThan0~1_cout\) # (!duty_cycle_reg_grip(1)))) # (!counter(1) & (!duty_cycle_reg_grip(1) & !\LessThan0~1_cout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000101011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => counter(1),
	datab => duty_cycle_reg_grip(1),
	datad => VCC,
	cin => \LessThan0~1_cout\,
	cout => \LessThan0~3_cout\);

-- Location: LCCOMB_X5_Y26_N20
\LessThan0~5\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~5_cout\ = CARRY((duty_cycle_reg_grip(2) & ((!\LessThan0~3_cout\) # (!counter(2)))) # (!duty_cycle_reg_grip(2) & (!counter(2) & !\LessThan0~3_cout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000101011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => duty_cycle_reg_grip(2),
	datab => counter(2),
	datad => VCC,
	cin => \LessThan0~3_cout\,
	cout => \LessThan0~5_cout\);

-- Location: LCCOMB_X5_Y26_N22
\LessThan0~7\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~7_cout\ = CARRY((counter(3) & ((!\LessThan0~5_cout\) # (!duty_cycle_reg_grip(3)))) # (!counter(3) & (!duty_cycle_reg_grip(3) & !\LessThan0~5_cout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000101011",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => counter(3),
	datab => duty_cycle_reg_grip(3),
	datad => VCC,
	cin => \LessThan0~5_cout\,
	cout => \LessThan0~7_cout\);

-- Location: LCCOMB_X5_Y26_N24
\LessThan0~9\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~9_cout\ = CARRY((counter(4) & (duty_cycle_reg_grip(4) & !\LessThan0~7_cout\)) # (!counter(4) & ((duty_cycle_reg_grip(4)) # (!\LessThan0~7_cout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => counter(4),
	datab => duty_cycle_reg_grip(4),
	datad => VCC,
	cin => \LessThan0~7_cout\,
	cout => \LessThan0~9_cout\);

-- Location: LCCOMB_X5_Y26_N26
\LessThan0~11\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~11_cout\ = CARRY((duty_cycle_reg_grip(5) & (counter(5) & !\LessThan0~9_cout\)) # (!duty_cycle_reg_grip(5) & ((counter(5)) # (!\LessThan0~9_cout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => duty_cycle_reg_grip(5),
	datab => counter(5),
	datad => VCC,
	cin => \LessThan0~9_cout\,
	cout => \LessThan0~11_cout\);

-- Location: LCCOMB_X5_Y26_N28
\LessThan0~13\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~13_cout\ = CARRY((counter(6) & (duty_cycle_reg_grip(6) & !\LessThan0~11_cout\)) # (!counter(6) & ((duty_cycle_reg_grip(6)) # (!\LessThan0~11_cout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001001101",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => counter(6),
	datab => duty_cycle_reg_grip(6),
	datad => VCC,
	cin => \LessThan0~11_cout\,
	cout => \LessThan0~13_cout\);

-- Location: LCCOMB_X5_Y26_N30
\LessThan0~14\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan0~14_combout\ = (counter(7) & (\LessThan0~13_cout\ & duty_cycle_reg_grip(7))) # (!counter(7) & ((\LessThan0~13_cout\) # (duty_cycle_reg_grip(7))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010101010000",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => counter(7),
	datad => duty_cycle_reg_grip(7),
	cin => \LessThan0~13_cout\,
	combout => \LessThan0~14_combout\);

-- Location: FF_X5_Y26_N31
pwm_out_reg_grip : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \slow_clk~clkctrl_outclk\,
	d => \LessThan0~14_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \pwm_out_reg_grip~q\);

-- Location: IOIBUF_X0_Y25_N1
\pwm_enable~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_pwm_enable,
	o => \pwm_enable~input_o\);
END structure;


